1. Field of the Invention
The present invention is in the field of semiconductor structures. The present invention is further in the field of semiconductor structures of transistor devices. The present invention further relates to the field of integrated power devices and circuits. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
The semiconductor transistor is the most important component for large integrated circuits. The complementary CMOS components used in current integrated circuit process technologies have undergone a continuous shrinking of the silicon area needed for elementary components, however the need to further improve on its general performance while reducing its cost is still a necessity that poses a significant challenge.
In particular, in the area of power integrated circuits the silicon area occupied by the power transistors and their performance is more and more important in several applications. A very critical parameter for power transistors in integrated circuits is their specific RDSon, measured in Ω*mm2. The silicon area is directly proportional to the cost of the integrated circuit and a low on-resistance is always desirable to increase the efficiency of the circuit and to reduce the power dissipation and therefore the temperature of the chip.
Typically the power transistors utilized in modern integrated circuits are constituted by large arrays of MOSFET and DMOS devices effectively connected in parallel. Generally these transistors are used in applications that require high currents. The efficiency of a device employing power transistors is increased by minimizing the power losses in the system. In particular for switching power converters the optimization of the process technology and of the semiconductor structures to match the electrical characteristics of the system is paramount to achieve high efficiency.
The most important Figure Of Merit (FOM) of a power transistor in specific power applications is the RDSon*Q of the transistor where RDSon is the on-resistance while Q is the charge associated with the gate capacitance (C*V). This FOM is directly associated with the time constant of the device. The lower the RDSon and the gate charge, the higher the achievable efficiency. In conventional CMOS technology, this FOM is independent from the silicon area since a lower RDSon deriving by an increase of the device size is generally correlated with an increase of the gate capacitance by the same amount.
On the other hand the cost in terms of occupied silicon area is a very important parameter and any method or technology to reduce the cost of the power device maintaining the same FOM (therefore increasing the current density per area) is very desirable. One means for increasing the current density is to increase the overall channel area of a transistor.
Generally the most studied prior art of semiconductor transistors that attempts to increase the equivalent gate area comprises MOSFET with single, double, triple and all-around gate or High Electron Mobility Transistors including III-V materials. The resistance offered by these devices when turned-on and their parasitic capacitances are very important to establish the device efficiency and speed.
Several prior art attempts to improve the control of the carrier transport in the device so as to effectively obtaining low on resistance components have been documented. Some of these examples include Takemura (U.S. Pat. No. 6,815,772), Mayer et al. (U.S. Pat. No. 5,497,019), and Hu et al. (U.S. Pat. No. 6,413,802). The general approach in the cited references is to add more control gate to the device in order to obtain a better Ion/Ioff ratio.
All these examples, however, require a much more complex and costly process involving usually Silicon On Insulator technology, which is still very expensive nowadays. A second problem is the alignment of the different gates of the device. Furthermore, since they are built on buried oxide, they cannot be used for power applications, since their capability to dissipate heat is very poor. Silicon dioxide, for example has a thermal conductivity that is about 100 times smaller than the one for Silicon. Finally, since their main objective is to enhance the control of the carrier transport, they are not very efficient in saving silicon area with respect to the conventional CMOS technology as explained in the following paragraph.
The typical cross-sections of a single and a double gate MOS are illustrated in FIG. 1 and FIG. 2. As it can be seen in a double gate MOS, aside the conventional gate, a second gate is present under the channel in order to improve the control of the channel modulation. In order to achieve the maximum control on the channel, the thickness of the channel region 16 is lower than the maximum extension xd of the depletion region in the channel region 16.
FIG. 3 shows a triple-gate MOS. This device has approximately the same performance of a double gate MOS, but it requires a simpler process technology since the alignment of the different gates is more easily achieved. However, differently from a double gate MOS, the channel width of a triple-gate MOS is limited. The distance between the two lateral gates must be smaller than the maximum extension of the depletion region. This limits the value of the horizontal dimension of the device. Furthermore, for process and cost related reasons, also the vertical dimension of the device is limited.
Another prior art example of enhanced control gate is the approach named “all-around gate MOS”. It is shown in FIG. 4. In this case, the gate terminal surrounds the whole channel, leading to an optimum channel control. However, also in this case, several physical and process limitations are present. In order to achieve the best control on the channel transport, the distance between parallel sidewalls of the device channel must be smaller than the maximum extension of the depletion region. This leads to a limit on the maximum extension of the total channel width.
Another interesting prior art attempt to achieve higher density for transistor devices is described in Hopper et al. (U.S. Pat. No. 7,435,628) and is reported in FIG. 5. In this case the gate 23 is in common between two transistors connected in parallel, and built facing each other, one on the left side of the gate and one on the right part of the gate. In this case the device is vertical and its drain 28 is formed under the channel and in the lower part of the structure as shown in FIG. 5. This configuration is therefore mainly used in discrete power devices.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits (switch mode power supplies for example). They are also called power devices or when used in integrated circuits, they are called power ICs. In the field of integrated power transistors one of the most important parameter is the RDSon*area of the utilized technology. The lower the RDSon*area, the lower is the cost of the device and the higher the speed of the transistor.
Although the cited prior art references describe structures that are not necessarily planar, they require complex process technologies and are not cost effective in solving the problem of obtaining transistors with lower on resistance per given silicon area in the power IC contest.
It is therefore a purpose of the present invention to describe a novel structure of a semiconductor transistor that offers the advantage of much higher density, reducing silicon area and cost combined with improved performances in terms of on resistance.